Books for Microwave and Optical Engineering

Text Books:
1. J.Y. Liao, “Microwave devices and circuits”, PHI Learning, 1987.
2. Gerd Keiser, “Optical Fiber Communications”, The McGraw Hill Companies, 4th Edition, 2008.
3. David Poser, Microwave Engineering, John Wiley, 3rd edition 2004.
4. John. D. Kraus, Antennas, McGraw Hill, 2nd Edition, 1998.

Reference Books:
1. K.C. Gupta, “Microwaves”, Wiley Eastern Ltd, 1983,
2. Annapoorna Das and Sisir K. Das, “Microwave Engineering”, TMH.
3. Anoop Singh, “Microwave Engineering”, PHI Learning, 2009.
4. R. F. Collins, “Foundation of Microwave Engineering”, McGraw Hill, 1987.
5. John. M. Senior, “Optical Fiber Communications Principles and Practice”, Second Edition, PHI, 1992.
6. Rajiv Ramaswami and Kumar N. Sivarajan, “Optical Networks – A Practical Curriculum & Syllabi B.Tech. Electronics & Communication Engineering Perspective”, Harcourt Publishers International Company, 2000.

Basic Questions in Electronics Circuits - II

1. Define positive feedback?

If the feedback signal is in phase with input signal, then the net effect of the

feedback will increase the input signal given to the amplifier. This type of feedback is

said to be positive or regenerative feedback.

2. Define negative feedback?

If the feedback signal is out of phase with the input signal then the input

voltage applied to the basic amplifier is decreased and correspondingly the output is

decreased. This type of feedback is known as negative or degenerative feedback.

3. Define sensitivity?

Sensitivity is defined as the ratio of percentage change in voltage gain with

feedback to the percentage change in voltage gain without feedback.

4. What are the types of feedback?

i. Voltage-series feedback

ii. Voltage-shunt feedback

iii. Current-series feedback

iv. Current-shunt feedback

5. Define feedback?

A portion of the output signal is taken from the output of the amplifier and is

combined with the normal input signal. This is known as feedback.

7. Give an example for voltage-series feedback.

The Common collector or Emitter follower amplifier is an example for

voltage series feedback.

11. What is Oscillator circuit?

A circuit with an active device is used to produce an alternating current is called

an oscillator circuit.

15. What are the conditions for oscillation?

The total phase shift of an oscillator should be 360o. For feedback oscillator it

should satisfies Barhausen criterion.

18. What is Miller crystal oscillator? Explain its operation.

It is nothing but a Hartley oscillator its feedback Network is replaced by a crystal.

Crystal normally generate higher frequency reactance due to the miller

capacitance are in effect between the transistor terminal.

20. Define Oscillator

A circuit with an active device is used to produce an alternating current is called

an oscillator circuit.

21. What is a tuned amplifier?

The amplifier with a circuit that is capable of amplifying a signal over a narrow band of

frequencies are called tuned amplifiers.

23. What happens to the circuit above and below resonance?

Above resonance the circuit acts as capacitive and below resonance the circuit acts as

inductive.

24. What are the different coil losses?

Hysteresis loss

Copper loss

Eddy current loss

25. What is Q factor?

It is the ratio of reactance to resistance.

26. What is dissipation factor?

It is referred as the total loss within a component i.e1/Q

27. What is the classification of tuned amplifiers?

Single tuned

Double tuned

Stagger tuned

28. What is a single tuned amplifier?

An n amplifier circuit that uses a single parallel tuned circuit as a load is called single

tuned amplifier.

29. What are the advantages of tuned amplifiers?

They amplify defined frequencies.

Signal to noise ratio at output is good

They are suited for radio transmitters and receivers

30. What are the disadvantages of tuned amplifiers?

The circuit is bulky and costly

The design is complex.

They are not suited to amplify audio frequencies.

31. What is neutralization?

The effect of collector to base capacitance of the transistor is neutralized by

introducing a signal that cancels the signal coupled through collector base capacitance.

This process is called neutralization.

32. What are double tuned amplifiers?

The amplifiers having two parallel resonant circuit in its load are called double tuned

amplifiers.

33. What is a stagger tuned amplifier?

It is a circuit in which two single tuned cascaded amplifiers having certain bandwidth are

taken and their resonant frequencies are adjusted that they are separated by an amount

equal to the bandwidth of each stage. Since resonant frequencies are displaced it is called

stagger tuned amplifier.

34. What are the advantages of stagger tuned amplifier?

The advantage of stagger tuned amplifier is to have better flat, wideband characteristics.

35. What are the advantages of double tuned over single tuned?

1. Possess flatter response having steeper sides

2. Provides larger 3 db bandwidth

3. Provides large gain-bandwidth product.

Matlab code for Satellite link design

CODING

clear all;

clc;

disp('ENTER UPLINK PARAMETERS')

disp('---------------------------------------')

pt=input('Earth station Transmitter output power :');

lbo=input('Earth Station back-off loss : ');

lbf=input('Earth station branching and feeder losses :');

at=input('Earth station Transmit antenna gain : ');

lu=input('Additional uplink atmospheric losses : ');

lp=input('Free-space path loss : ');

gte=input('Satellite receiver G/Te ratio : ');

bfb=input('Satellite branching and feeder losses : ');

br=input('Bit rate : ');

disp('---------------------------------------')

disp('ENTER DOWNLINK PARAMETERS')

disp('---------------------------------------')

disp('')

pt2=input('Satellite transmitter output power :');

lbo2=input('Satellite back-off loss : ');

lbf2=input('Satellite branching and feeder losses :');

at2=input('Satellite Transmit antenna gain : ');

ld=input('Additional downlink atmospheric losses : ');

lp2=input('Free-space path loss : ');

gte2=input('Earth station receiver G/Te ratio : ');

bfb2=input('Earth station branching and feeder losses : ');

br2=input('Bit rate : ');

disp('---------------------------------------')

EIRP=pt+at-lbo-lbf;

disp('UPLINK BUDGET')

disp('---------------------------------------')

%EIRP (Earth Station)

fprintf('EIRP (Earth Station) = %f dBW \n',EIRP);

c1=EIRP-lp-lu;

%Carrier power density at the satellite antenna :

fprintf('Carrier power density at the satellite antenna = %f dBW\n',c1);

cn0=c1+gte-(10*log10(1.38*(10^(-23))));

fprintf('C/No at the satellite = %f dB\n',cn0);

ebn0=cn0-(10*log10(br));

fprintf('Eb/No : = %f dB\n',ebn0);

cn=ebn0-10*(log10((40*(10^6))/(br)));

fprintf('for a minimum bandwidth system, C/N = %f dB\n',cn);

disp('---------------------------------------')

disp('DOWNLINK BUDGET')

disp('---------------------------------------')

%EIRP (satellite transponder)

EIRP2=pt2+at2-lbo2-lbf2;

fprintf('EIRP (satellite transponder) = %f dBW \n',EIRP2);

c12=EIRP2-lp2-ld;

%Carrier power density at the earth station antenna :

fprintf('Carrier power density at earth station antenna = %f dBW\n',c12);

cn02=c12+gte2-(10*log10(1.38*(10^(-23))));

fprintf('C/No at the earth station receiver = %f dB\n',cn02);

ebn02=cn02-(10*log10(br2));

fprintf('Eb/No : = %f dB\n',ebn02);

cn2=ebn02-10*(log10((40*(10^6))/(br2)));

fprintf('for a minimum bandwidth system, C/N = %f dB\n',cn2);

a=10^(ebn0/10);

b=10^(ebn02/10);

ebn0all=(a*b)/(a+b);

ebn02db=10*log10(ebn0all);

fprintf('Eb/No(overall) : = %f dB\n',ebn02db);

 SAMPLE INPUT 

ENTER UPLINK PARAMETERS

---------------------------------------

Earth station Transmitter output power :33

Earth Station back-off loss : 3

Earth station branching and feeder losses :4

Earth station Transmit antenna gain : 64

Additional uplink atmospheric losses : .6

Free-space path loss : 206.5

Satellite receiver G/Te ratio : -5.3

Satellite branching and feeder losses : 0

Bit rate : 120*(10^6)

---------------------------------------

ENTER DOWNLINK PARAMETERS

---------------------------------------

Satellite transmitter output power :10

Satellite back-off loss : .1

Satellite branching and feeder losses :.5

Satellite Transmit antenna gain : 30.8

Additional downlink atmospheric losses : .4

Free-space path loss : 205.6

Earth station receiver G/Te ratio : 37.7

Earth station branching and feeder losses : 0

Bit rate : 120*(10^6)

OUTPUT

---------------------------------------

UPLINK BUDGET

---------------------------------------

EIRP (Earth Station) = 90.000000 dBW

Carrier power density at the satellite antenna = -117.100000 dBW

C/No at the satellite = 106.201209 dB

Eb/No : = 25.409397 dB

for a minimum bandwidth system, C/N = 30.180609 dB

---------------------------------------

DOWNLINK BUDGET

---------------------------------------

EIRP (satellite transponder) = 40.200000 dBW

Carrier power density at earth station antenna = -165.800000 dBW

C/No at the earth station receiver = 100.501209 dB

Eb/No : = 19.709397 dB

for a minimum bandwidth system, C/N = 24.480609 dB

Eb/No(overall) : = 18.674255 dB

>> 

Network Analysis and Theorems - Simply explained

PART 1

The fundamental laws that govern electric circuits are the Ohm’s Law and the Kirchoff’s Laws.

• Ohm's law
• Kirchoff's Current law
• Kirchoff's Voltage law
• Superposition Theorem
• Thevenin’s Theorem (or Helmholtz’s Theorem)
• Norton’s Theorem
• Reciprocality Theorem
• Compensation Theorem
• Maximum Power Transfer Theorem
• Millmann’s Theorem
• Rosen’s Theorem (Nodal-Mesh Transformation Theorem)

Click to download

PART 2

Network Analysis - Practically Explained and self learn [Click to download]

In Plant Training Report - DOWNLOAD REPORT

 REPORT 1

In-plant training-1 [ ALL INDIA RADIO]
In-plant training-2 [DOORDARSHAN]
In-plant training-3 [MANATEC ELECTRONICS]

Get Report

 REPORT 2

1. ALL INDIA RADIO
2. BHARATH SANCHAR NIGAM LIMITED
3. AUROTRONICS PRIVATE LIMITED
4. ELECTRICITY DEPARTMENT

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Sankalp Semiconductor Campus Recruitment 2011

Campus Recruitment 2011

Sankalp Semiconductor Private Ltd is an Analog, Mixed Signal and RF semiconductor service provider with the mission to serve worldwide customers with Benchmark Quality and Time to Market by means of methodology innovations and automations. Founded by a team of Analog and Mixed Signal IC Professionals who bring more than 40 years of collective experience in the IC industry, Sankalp Semiconductor holds a unique ability to tackle complex design/layout challenges by means of state-of-the-art methodology solutions.

Sankalp's endeavor is an effort towards creating a value based organization where the values and culture are embedded deep into the sub-conscience of the individuals and where they are nurtured into becoming world leaders and entrepreneurs with conscience. Our motto is to create Entrepreneurs with Conscience.

Openings

For the year 2011, Sankalp Semiconductor Private Limited is looking for highly passionate

1.      Graduate Engineers from the field of Electronics, Electronics & Communications, Electrical and Instrumentation stream.

2.      Post Graduate Engineers from the field of VLSI.

Eligibility Criteria – 70% aggregate or 7.5 CGPA and at all levels.

The pay package (CTC) for the year 2011 joiners will be 3.3LPA.

Designation – Design Engineer

Job Profile - Will be working on Analog & Mixed Signal Layout & Design.

Scope – Continuous accelerated learning is the Mantra in Sankalp. When learning ceases, growth stops, and the individual ceases to grow. With our motto to create Entrepreneurs with Conscience, we let it start with Intrapreneurship (An Entrepreneur within Sankalp). Assets in Sankalp are empowered to take the right decisions for the Company. Multi-dimensional growth of the assets is Sankalp’s goal. Sankalp is for people with long term commitment.

Selection Procedure

Sankalp’s selection procedure will have the following procedure in that order. Sequential clearing of each round leads to qualifying to the next round.

1. Written test
2. Technical Interview
3. Group Discussion
4. HR interview

Written test

The written test will be for one hour duration having two sections Technical (covering basic circuits with R, L, C, V, I, CMOS and Electronics) and Aptitude (Geometric & General). Minimum 50% score in both are pre requisite to qualify for the other rounds.

 
The participants are expected to bring with them

1. One Passport size photo of self.
2. One resume in hardcopy.
3. Pen, pencil, erasers to write the tests.
4. Calculators are permitted.

The written test will be followed by Group Discussion, Technical interview round and HR interview in that order on clearing each of them. Failing any round leads to elimination from selection.

In the event of us deciding to have the HR round at our Hubli centre, the same will be notified with dates.

Basic Placement Preparation questions in VLSI

1)      What is drain punch through?

2)      What is the difference between trans-conductance and output conductance?

3)      How can switching delays be reduced?

4)      What is “class-A current” or “power supply crow-barring”?

5)      What is miller effect?

6)      What is latch up in CMOS circuits? Why does it occur?

7)      What are lambda rules?

8)      What is wiring capacitance?

9)      What is substrate doping?

10)   What is channelling effect?

11)   What is the difference between stick diagrams and layout?

12)   What are the different masks used in CMOS fabrication?

13)   What is rise time and fall time delay? What are the expressions for calculations of the same for inverters?

14)   What does Speed versus area Trade off explain?

15)   What is logical effort and path logical effort?

16)   What is electrical effort and path electrical effort?

17)   How do u minimise delay in an inverter cascade?

18)   What is the general form of a BiCMOS circuit? Explain how this design can be extended to other CMOS networks (Universal Gates).

19)   Compare gate delay versus external load capacitance features of CMOS and BiCMOS.

20)   What are mirror circuits? When can they be applied? Explain the advantages of mirror circuits over others.

21)   What is pseudo-NMOS? Why is it called ratioed logic? What are the advantages and disadvantages?

22)   What is the difference between tri-state ad clocked CMOS circuits?

23)   How does charge leakage problem occur?

24)   Explain the terms precharge and evaluation with respect to dynamic logic gate.

25)   What is charge sharing?

26)   What is domino logic?

27)   What is a BiCMOS driver?

28)   Why super buffers are used in nMOS technology?

29)   Give two constraints for choosing of layers in MOS?

30)   What is a pass transistor?

31)   What is an nMOs inverter?

32)   What’s the significance of stick diagram?

33)   In stick diagram what does green colour indicate?

34)   What is sheet resistance?

35)   How do you represent a n type and p type transistor in CMOS design?

36)   What is the minimum distance between metal1 and metal 2, according to Lambda based rules?

37)   Explain gate design for transient performance?

38)   What are the limits of miniaturization?

39)   What is depletion width?

40)   What  are limits due to subthreshold currents and limits due to current density?

41)   What is regularity?

42)   What is crosstalk?

43)   How can charge sharing/leakage be minimised?

44)   What is dual rail network?

45)   What does logical effort signify?

46)   What is impurity scattering?

47)   What is noise margin?

48)   What are weak FET's?

49)   Are there any other design rules other than lamda based rules?

50)   When do body bias effects occur?

51)   Why don’t we use just one NMOS or PMOS transistor as a transmission gate?

52)   Why do we gradually increase the size of inverters in buffer design? Why not givethe output of the circuit to one large inverter?

53)   How is delay affected if we increase the load capacitance?

54)   How is delay affected incase we put a resistance at CMOS circuit output?

55)   How does the resistance of metal line change with increase in length and thickness?

56)   How can we reduce the power consumption for CMOS logic?

57)   How can u calculate the delay in the case of CMOS circuit?

58)   Why do we use small transistor in parallel in the case of big inverter?

59)   What happens if we use an inverter instead of the differential sense amplifier?

60)   What is the critical path in SRAM?

61)   Which is the basic material of VLSI design started & why?

62)    While VLSI designing, if we don’t want involve the impurities properties, which is the best process for that?

63)    Why  crystal materials are used?

64)    What is pinch off?

65)    What is diffusion?

66)    In VLSI designing which type of switch is most preferable?

67)    Why required bubble & how to fabricate?

68)    What do mean by resolution?

69)    What is the compound gate?

70)    Which designing the multiplexer and demultiplexer which type of transistor is more preferable and why?

71)    What is pull down and pull up resister and     why it is required while fabricating?

72)    What is RISC process?

73)    Stands for RISC?

74)    What are the draw back of CMOS and nMOS IC?

75)    Why enhancement type is preferable?

76)    What are the advantages CMOS of IC?

77)    Why CMOS is preferable?

78)    Why CMOS is required?

79)    Which type of transistor is preferable while designing the VLSI IC and why?

80)    What do mean by threshold voltage? How it is to be utilized?

81)    Layout of designing is on which base& why? How its applicable & what is that process?

82)    Why nMOS & pMOS type is preferable & specify enhancement type transistor?

83)    What base source, drain and gate will be decided & why? If required to reduce the losses what will you do? Then which is process to reduce the losses?

84)     Why oxide layer is required?

85)    Why super buffers are used in nMOS technology?

86)    In inverter circuit what is meant by Zp.u & Z p.d?

87)    Why stick diagrams are used?

88)    Which type of transistors   is more preferable for stick diagram and why?

89)    Which is the best process of analyzing the logic  verification?

90)   The transmission gate is called _____________ switch

91)   What are the fall time and rise time of an inverter?

92)   In a symmetric inverter the dimension of n-FET is ___ time of p-FET.

93)   Write the expression for mid-point voltage of inverter.

94)   __________ circuits are used to get the symmetrical layouts of the gates.