Saturday, May 28, 2011
Basic Placement Preparation questions in VLSI
1) What is drain punch through?
2) What is the difference between trans-conductance and output conductance?
3) How can switching delays be reduced?
4) What is “class-A current” or “power supply crow-barring”?
5) What is miller effect?
6) What is latch up in CMOS circuits? Why does it occur?
7) What are lambda rules?
8) What is wiring capacitance?
9) What is substrate doping?
10) What is channelling effect?
11) What is the difference between stick diagrams and layout?
12) What are the different masks used in CMOS fabrication?
13) What is rise time and fall time delay? What are the expressions for calculations of the same for inverters?
14) What does Speed versus area Trade off explain?
15) What is logical effort and path logical effort?
16) What is electrical effort and path electrical effort?
17) How do u minimise delay in an inverter cascade?
18) What is the general form of a BiCMOS circuit? Explain how this design can be extended to other CMOS networks (Universal Gates).
19) Compare gate delay versus external load capacitance features of CMOS and BiCMOS.
20) What are mirror circuits? When can they be applied? Explain the advantages of mirror circuits over others.
21) What is pseudo-NMOS? Why is it called ratioed logic? What are the advantages and disadvantages?
22) What is the difference between tri-state ad clocked CMOS circuits?
23) How does charge leakage problem occur?
24) Explain the terms precharge and evaluation with respect to dynamic logic gate.
25) What is charge sharing?
26) What is domino logic?
27) What is a BiCMOS driver?
28) Why super buffers are used in nMOS technology?
29) Give two constraints for choosing of layers in MOS?
30) What is a pass transistor?
31) What is an nMOs inverter?
32) What’s the significance of stick diagram?
33) In stick diagram what does green colour indicate?
34) What is sheet resistance?
35) How do you represent a n type and p type transistor in CMOS design?
36) What is the minimum distance between metal1 and metal 2, according to Lambda based rules?
37) Explain gate design for transient performance?
38) What are the limits of miniaturization?
39) What is depletion width?
40) What are limits due to subthreshold currents and limits due to current density?
41) What is regularity?
42) What is crosstalk?
43) How can charge sharing/leakage be minimised?
44) What is dual rail network?
45) What does logical effort signify?
46) What is impurity scattering?
47) What is noise margin?
48) What are weak FET's?
49) Are there any other design rules other than lamda based rules?
50) When do body bias effects occur?
51) Why don’t we use just one NMOS or PMOS transistor as a transmission gate?
52) Why do we gradually increase the size of inverters in buffer design? Why not givethe output of the circuit to one large inverter?
53) How is delay affected if we increase the load capacitance?
54) How is delay affected incase we put a resistance at CMOS circuit output?
55) How does the resistance of metal line change with increase in length and thickness?
56) How can we reduce the power consumption for CMOS logic?
57) How can u calculate the delay in the case of CMOS circuit?
58) Why do we use small transistor in parallel in the case of big inverter?
59) What happens if we use an inverter instead of the differential sense amplifier?
60) What is the critical path in SRAM?
61) Which is the basic material of VLSI design started & why?
62) While VLSI designing, if we don’t want involve the impurities properties, which is the best process for that?
63) Why crystal materials are used?
64) What is pinch off?
65) What is diffusion?
66) In VLSI designing which type of switch is most preferable?
67) Why required bubble & how to fabricate?
68) What do mean by resolution?
69) What is the compound gate?
70) Which designing the multiplexer and demultiplexer which type of transistor is more preferable and why?
71) What is pull down and pull up resister and why it is required while fabricating?
72) What is RISC process?
73) Stands for RISC?
74) What are the draw back of CMOS and nMOS IC?
75) Why enhancement type is preferable?
76) What are the advantages CMOS of IC?
77) Why CMOS is preferable?
78) Why CMOS is required?
79) Which type of transistor is preferable while designing the VLSI IC and why?
80) What do mean by threshold voltage? How it is to be utilized?
81) Layout of designing is on which base& why? How its applicable & what is that process?
82) Why nMOS & pMOS type is preferable & specify enhancement type transistor?
83) What base source, drain and gate will be decided & why? If required to reduce the losses what will you do? Then which is process to reduce the losses?
84) Why oxide layer is required?
85) Why super buffers are used in nMOS technology?
86) In inverter circuit what is meant by Zp.u & Z p.d?
87) Why stick diagrams are used?
88) Which type of transistors is more preferable for stick diagram and why?
89) Which is the best process of analyzing the logic verification?
90) The transmission gate is called _____________ switch
91) What are the fall time and rise time of an inverter?
92) In a symmetric inverter the dimension of n-FET is ___ time of p-FET.
93) Write the expression for mid-point voltage of inverter.
94) __________ circuits are used to get the symmetrical layouts of the gates.